1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the invention is applicable to the formation of a floating-gate type memory cell in the manufacture of a non-volatile semiconductor memory.
2. Description of the Related Art
Recently, as a result of successful materialization of non-volatile memory units incorporating vast memory capacity, contraction of the dimension of memory cell and the data writing time is strongly urged among the concerned. To solve this problem, a proposal has been raised on the "diffusion self-aligned" (hereinafter called "DSA") structure from the standpoint of the structure of the memory cell. FIG. 1 designates a conventional non-volatile memory presented for explaining the DSA structure. The reference numeral 11 designates a P-type silicon substrate, 12 oxidized film for separation, 13a a source region containing N.sup.+ type impurities, 13b a drain region containing N.sup.+ type impurities, 14 a floating gate, 15 a control gate, 16 a region containing P type impurities, 17 a channel region, 18 a gate insulation film, and 19 designates an insulation film between gate electrodes, respectively. As shown in FIG. 1, according to the DSA structure, the region 16 containing P type impurities having density stronger than that is present in the center of the channel region 17 is provided. The region 16 is hereinafter merely called the "P-pocket" region. In writing data a provision of the P-pocket region 16 promotes intensity of electric field of the channel region 17 adjacent to the drain region 13b to allow more amount of current to flow into the floating gate 14. In particular, there is a problem inherent in the floating gate type cell transistor in terms of the resistance of the cell transistor against "punch-through" effect. Concretely, when a floating gate type field effect transistor is made available for the cell, on the way of feeding a voltage to the drain region 13b, due to capacitive coupling effect between the floating gate 14 and the drain region 13b, the potential of the floating gate 14 is lifted. As a result, unlike any single-gate type transistor, the "punch-through" effect can easily be applied to the cell transistor. The shorter the length of the gate of transistor, the easier the occurrence of this phenomenon. Actually, this makes up the most critical problem among the concerned in the effort to contract the size of the cell transistor. On the other hand, a provision of the "P-pocket" region 16 suppresses expansion of depletion, thus promoting the resistance of the cell transistor against occurrence of the "punch-through" phenomenon. This in turn advantageously promotes contraction of the size of the cell.
Due to the above reason, application of the DSA structure to the formation of the floating type memory cell transistor accelerates the speed of writing data in it, and yet, promotes the resistance of this cell transistor against occurrence of the "punch-through" phenomenon, and therefore, the DSA structure is quite essential for such a large-capacitive non volatile memory today.
In order to fully generate the proper function of an N-channel type cell transistor incorporating the DSA structure mentioned above, profile of the density of impurities in the P-pocket region 16 adjacent to an edge of the drain region 13b of the floating gate is particularly important. To securely promote the resistance of the cell transistor against the "punch-through" phenomenon and accelerate the data writing speed, the density of impurities in the P-pocket region 16 close to an edge of the drain region 13b must constantly be held stronger than that is present in the channel region 17. Nevertheless, since the P-pocket region 16 is formed by means of P-type impurities aided by injection of ions after completing the formation of stratified gate electrodes, it results in the occurrence of a problem described below.
The edge of the drain 13b is covered with stacked gate electrodes. When injecting ions by applying a conventional ion injection method, in order to prevent occurrence of "channeling effect", in other words, in order to prevent ion from being injected beyond a path which allows easy passage of ions, only a maximum of 7 degrees of angle is applied to the injection of ions against the normal of the silicon substrate 11, and thus, the P-type impurities cannot fully be injected into the region close to the drain region 13b below the floating gate 14. Because of this, actually, any conventional art injects ions needed for the formation of the P-pocket region 16, and then executes an annealing process to diffuse the P-type impurities into such region farther than the edge of the drain region 13b below the channel region 17 before eventually injecting ions needed for the formation of the source and drain regions 13a and 13b. In this case, an additional round of annealing process is needed for the formation of the P-pocket region 16 containing the DSA structure.
Because of this additional annealing process, the conventional art cannot simultaneously execute the double ion injection processes, and yet, an additional round of patterning process must also be executed. When providing the P-pocket region 16 by diffusing the P-type impurities as mentioned above, profile of the density of impurities cannot perfectly be controlled, and yet, enough density of the P-type impurities cannot be generated in such region close to the drain region 13b. Furthermore, the annealing process needed for the formation of the P-pocket region 16 gravely affects the profile of the density of the P-type impurities. Furthermore, when providing the P-pocket region 16, in order to thermally diffuse the P-type impurities in the lateral direction to full extent and maintain enough density of the impurities in the diffused region, a substantial dose of ion must be injected. This in turn expands capacity at junctions and weakens the junction breakdown voltage. In particular, the junction breakdown voltage is determined by the breakdown voltage of a high P-type impurity region formed of the overlapping portions the P-pocket region and a channel stopper region located below an isolation region, and by the breakdown voltage of the pn junction formed between the N.sup.+ regions of the regions 13a and 13b. Because of this, the junction breakdown voltage is largely dependent on the distribution of the density of impurities present in those adjacent regions.